1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having an improved wiring structure and a method of manufacturing the same.
2. Description of the Related Art
Recently, miniaturization and high integration of elements are large subjects in a semiconductor integrated circuit in which its capacity is increased and advanced functions are employed. As an example of a conventional technique, an erasable and electrically programmable read only memory cell having a floating gate, i.e., an EPROM will be described below.
FIG. 1 is a plan view showing a portion of a conventional EPROM memory cell. FIG. 2 is a sectional view taken along lines D-D' of FIG. 1. In an EPROM cell, similarly to an ordinary MOS type FET, a drain region 8 and a source region 9 are provided separately through a channel region 15 on the surface of a semiconductor substrate 11. A floating gate 7 is so provided on the channel region 15 through a first gate insulating film 16 as to be completely insulated from the periphery. A control gate 1 is provided on the floating gate 7 through a second gate insulating film 17. The respective drain regions 8 and channel regions 15 are insulated by element isolating regions 5 to form cells, and the source regions 9 are so aligned in a direction perpendicular to the element isolating regions 5 as to hold the respective drain regions 8 and channel regions 15. The control gates run in parallel on the respective channel regions 15, and slits 6 of projections of the control gates 1 are disposed on the element isolating regions 5. The slit 6 is disposed under the control gate 1 of a slit region 61 on the element isolating region 5 to isolate the floating gate 7 on the channel region 15 of each cell. The portion of the slit region 16 except the control gate 1 of the slit region 61 is filled with an interlayer insulating film 18. Bit lines 2 and source lines 3 are formed in parallel with each other in a direction perpendicular to the control gates 1 and the source regions 9 on the substrate 11, the bit lines 2 are electrically conducted with the respective drain regions 8 in contact holes 4, and the source lines 3 are electrically conducted with the source region 9. An aluminum Al or an alloy in which silicon Si, copper Cu, etc., are added to the aluminum Al, is used as wirings of connections between elements, the bit lines 2, the source lines 3, etc., and the wirings are conducted with the drain regions 8 and the source regions 9 through the contact holes 4.
However, since the contact hole 4 indispensably needs a predetermined size so as to form a preferable contact, as understood from FIG. 1, the presence of the contact holes 4 disturbs miniaturization of the elements. Further, when the integration of a semiconductor integrated circuit is improved, total length of the wirings is increased, whereas the width of the wirings is narrowed, its current density is increased, and aspect ratio of the contact holes is increased. Thus, the wirings become weak against heat and electric stress, and problems such as wire disconnection, and a decrease in reliability arise.